The present invention is related to logic circuitry, and more particularly to test enabled flip-flops.
As shown in FIG. 1, a semiconductor device 100 includes a number of I/O buffers 110, 120 that are available for bringing input signals 125 onto a chip 140, and for providing output signals 150 to off chip recipients. The input signals 125 are provided to a core logic block 130, and the output signals 115 are driven by core logic block 130. Over the years various testing schemes and/or approaches have been developed to verify semiconductor devices such as that shown in FIG. 1.
As shown in FIG. 2, prior testing methodologies have extended the functionality of core logic 130 to include a multiplexer 260 and a multiplexer 270. Multiplexers 260, 270 provide an ability to select a test mode via a test select input 271, and to select one of many test modes 250 using a mode select input 261. In particular, mode select input 271 drives a selector input of multiplexer 260 such that one of test inputs 251, 252, 253, 254, 255 are selected to drive a test output 262. Test mode input 271 drives a selector input of multiplexer 270 such that one of a standard operational output 263 or test output 262 is selected to drive output 115 via an output buffer 272. As will be appreciated, testing core logic 130 includes providing a signal from core logic 130 (one of signals 251, 252, 253) to output 115 via five input multiplexer 260, two input multiplexer 270, and output buffer 272. Assuming the test signal is being driven by core logic 130 and includes some delay there from, the propagation time of a test signal and that of a standard signal are represented by the following equation:TestDelay=CoreDelay+Mux 260Delay+Mux 270Delay+Output BufferDelay,StandardDelay=CoreDelay+Mux 270Delay+Output BufferDelay.It should be noted that Mux 260Delay increases as a function of the number of implemented test modes. The previously described delay may be too large for some upcoming devices that rely on very high clock frequencies to perform the designed functionality.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for facilitating semiconductor testing.